Nikolaos Rapanis
Computer & Electrical Engineering. I work across the stack that decides how a chip spends its power budget — from RTL and silicon up through the control policy that tells it when to sprint.
I'm an undergraduate researcher on the TauMat project under Professor Ben Lee, an NSF SBIR Phase II–funded partnership studying CPU power and thermal behavior — building the testing infrastructure and telemetry pipeline behind a reinforcement-learning-based dynamic sprinting policy.
Outside research, I design analog and digital circuits (transimpedance amplifiers, SRAM arrays, a pipelined RV32IM processor), and I'm minoring in Engineering Entrepreneurship. I TA for Penn's intro CS and computer systems courses, and I'm building out a ML-based tennis shot outcome predictor on the side.
skills
Hardware & Circuit Design
Systems & Low-Level
Embedded
Programming
Data & ML
experience
Undergraduate Researcher — Dynamic Sprinting & Thermal Modeling (TauMat)
- Build and maintain testing infrastructure (Python, Bash) for CPU power/thermal benchmarking, including telemetry collection via perf and turbostat.
- Design experiments to identify system limitations and operating boundaries, informing candidate model approval and generating data behind an RL-based power optimization policy.
- Present findings to industry partner and cross-functional team (PhD lead, faculty advisor, fellow researcher) in biweekly meetings.
Course Development Assistant — Engineering Economics
- Design course materials — homework, quizzes, rubrics, capstone projects — for a new Engineering Economics course.
- Review recorded lectures and suggest edits, reducing revision cycles by ~35%.
Teaching Assistant — CIS 1100, CIS 2400, ESE 3190
- Lead recitations, develop and grade exams, and host office hours for 80–200+ students across programming and computer systems courses.
- Evaluate assignments spanning Python programs, RISC-V processor implementations, and CMOS circuit designs.
projects
Live Tennis Shot Outcome Predictor
in progressA computer-vision pipeline predicting shot outcomes live from broadcast video, court and ball tracking through to a bounce classifier.
16×4 SRAM Memory Design
A 16×4 SRAM array in 45nm CMOS — 6T bitcells, decoder, and precharge — at 90.88ps worst-case delay.
Wideband Trans-Impedance Amplifier
A 4-stage TIA in 45nm CMOS hitting 507kΩ gain and 359MHz bandwidth on a 1V supply.
Pipelined RV32IM Processor
A 5-stage pipelined RV32IM core in SystemVerilog with hazard detection, forwarding, and branch prediction.
Embedded MIDI Transposer: Music to My Ears
An ATmega328PB embedded system that receives live MIDI, transposes by semitones, and replays it in real time.
Analog Metal Detector with Beat-Frequency Detection
Dual LC-oscillator metal detector with custom PCB, tuned for a clean audible beat-frequency shift.
Stack-Based Language to RISC-V Compiler
A compiler in C translating a stack-based language to RISC-V assembly, with a hand-written lexer and code generator.
contact
Open to conversations about hardware, systems, and power-aware computing — or anything adjacent. Reach out directly.